OpenCL_helpers/Makefile

-include makefile.init
#-include makefile.defs
RM := rm -rf
CC := gcc
LINKER := gcc
CFLAGS := -std=c11 -pedantic -Wall -Wextra -Wconversion
LDFLAGS := -L/usr/local/cuda/lib64 -L/opt/intel/opencl/lib64
OUTPUTFLAGS := -c -fmessage-length=0
MISCFLAGS := -pthread
INCLUDES := -I"src/include_h/" -I"src/include_hd/" \
            -I"/usr/local/cuda/include"
DEFS :=
# for debug
MODEFLAGS := -O0 -g3
TARGETDIR := build/Debug
# for release
### MODEFLAGS := -O3
### TARGETDIR := build/Release
# All of the sources participating in the build are defined here
# -include sources.mk
OBJS :=
C_DEPS :=
# Every subdirectory with source files must be described here
SRCDIR := src
# -include subdir.mk
# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += $(wildcard $(SRCDIR)/*.c)
#OBJS += $(wildcard $(TARGETDIR)/*.o)
OBJS += $(patsubst $(SRCDIR)/%.c,$(TARGETDIR)/%.o,$(C_SRCS))
C_DEPS += $(wildcard $(TARGETDIR)/*.d)

OCLH_BUILDER_NAME  := oclh_br
OCLH_COMPILER_NAME := oclh_cr
OCLH_LINKER_NAME   := oclh_lr
OCLH_LIBRARY_NAME  := liboclh.so

# Each subdirectory must supply rules for building sources it contributes
$(TARGETDIR)/%.o: $(SRCDIR)/%.c
	@echo 'Building file: $<'
	@echo 'Invoking: GCC C Compiler'
	mkdir -p $(TARGETDIR); \
	$(CC) $(INCLUDES) $(MODEFLAGS) $(CFLAGS) $(DEFS) $(OUTPUTFLAGS) \
	-MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" \
	-o "$@" "$<"
	@echo 'Finished building: $<'
	@echo ' '
# -include objects.mk
USER_OBJS :=
LIBS := -lOpenCL

ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
endif
# Add inputs and outputs from these tool invocations to the build variables 
# All Target
all: oclh_builder
# Tool invocations
oclh_builder: DEFS= -D__OCLH_BUILDER_FLAG -D__OCLH_BUILD_LOG_TO_STDOUT_FLAG
oclh_builder: OUTPUTNAME=$(OCLH_BUILDER_NAME)
oclh_builder: $(OBJS) $(USER_OBJS)
	@echo 'Building target: $@'
	@echo 'Invoking C Linker'
	$(LINKER) $(LDFLAGS) $(MISCFLAGS) $(LIBS) \
	-o "$(TARGETDIR)/$(OUTPUTNAME)" $(OBJS) $(USER_OBJS)
	@echo 'Finished building target: $@'
	@echo ' '
# Other Targets
clean:
	$(RM) $(OBJS)$(C_DEPS) \
	$(TARGETDIR)/$(OCLH_BUILDER_NAME) \
	$(TARGETDIR)/$(OCLH_COMPILER_NAME) \
	$(TARGETDIR)/$(OCLH_LINKER_NAME) \
	$(TARGETDIR)/$(OCLH_LIBRARY_NAME)
	@echo ' '

.PHONY: all clean dependents

-include makefile.targets